How Microchips Are Made: The Complete CPU Fabrication Process Step by Step

// Semiconductor Manufacturing · CPU Fabrication · 2026 · 4,100 words · 4 interactive labs · April 2026

How Microchips Are Made:
The Complete CPU
Fabrication Process
Step by Step

The CPU inside your laptop contains more than 30 billion transistors, each smaller than a coronavirus, manufactured with tolerances measured in atomic diameters, inside buildings that cost $20 billion to construct and must be cleaner than any hospital operating room by a factor of 10,000. Understanding how this is possible is one of the most fascinating engineering stories in human history.

Read the Deep Dive ↓ Open Fab Lab 🔬 Silicon Wafer → Transistors → Dies → CPUs EUV Photolithography · ASML 3nm FinFET · GAA · Yield Management // Table of Contents

1. What's Inside a CPU? Transistors & FinFETs
2. Photolithography & EUV Explained
3. Deposition, Etching & Ion Implantation
4. Silicon Wafer Manufacturing
5. Wafer Testing & Chip Binning
6. The Complete Fabrication Flow

In a building on the outskirts of Hsinchu, Taiwan, workers in full white bunny suits — head-to-toe contamination suits, gloves, and respirators — move with deliberate slowness through a room with 500 air changes per hour. The air inside is filtered to allow fewer than 1 particle per cubic foot. For comparison, a hospital operating room allows 10,000. Outside, in the normal air you're breathing right now, there are about 35 million particles per cubic foot. This is a cleanroom — specifically, it's one of TSMC's N3 fabrication lines, manufacturing the 3-nanometer chips that will end up inside next year's iPhones, MacBooks, and AI accelerators. What happens inside this building, repeated billions of times across tens of thousands of wafers per month, is the most precise manufacturing process humanity has ever devised.

Most engineers who use CPUs and GPUs daily have a vague understanding of how chips are made — "something with silicon and light." This guide is the detailed version. We'll walk through every major step of the fabrication process, from raw silicon wafer to packaged processor, with the technical depth that actually helps you understand why these chips cost what they cost and why building a new fab takes $20 billion and five years.

// 01What's Inside a CPU: Transistors, FinFETs, and 30 Billion Switches

Everything inside a modern CPU is built from transistors — semiconductor devices that function as electrically controlled switches. When a transistor is "on," current flows through it; when it's "off," current doesn't. By arranging billions of these switches in specific configurations (logic gates, memory cells, arithmetic units), engineers build circuits that can perform complex calculations, store data, and execute instructions. The Apple M3 has approximately 25 billion transistors. The Nvidia H100 GPU has 80 billion. All of modern computing emerges from the precise switching behavior of these atomic-scale devices.

The conventional planar transistor dominated chip design from the 1950s through the 2000s — a simple three-terminal device where a gate electrode controlled current flow in a thin channel beneath it. As process nodes shrank below 22nm, this planar design hit a fundamental problem: leakage current. When transistors are nanometers apart and the gate is as thin as a few atoms, electrons tunnel through the supposedly-insulating gate oxide through quantum mechanical effects, causing energy waste and heat generation even when the transistor is "off." Intel's solution, commercialized in 2011 at 22nm and now universal across the industry, was the FinFET (Fin Field-Effect Transistor).

A FinFET raises the channel material into a thin vertical "fin" — a 3D protrusion of silicon — and wraps the gate around three sides of this fin. Instead of a gate controlling current through a flat channel beneath it (one control surface), the gate now surrounds the fin on three sides (three control surfaces). This dramatically improves the gate's ability to control the channel, reducing leakage by orders of magnitude. The fin's narrow width also physically prevents charge from distributing away from the gate's control region. Current advanced process nodes at TSMC, Samsung, and Intel use FinFETs at 5nm and 3nm, while the next transition is to Gate-All-Around (GAA) transistors — where the gate wraps the channel on all four sides, using stacked horizontal "nanosheets" of silicon. Samsung's 3nm GAA node and TSMC's 2nm node both use this architecture.

💡 "nm" Process Nodes Are Marketing, Not Physics

Here's the thing most chip articles miss: the "nm" number in modern process node names (TSMC 3nm, Intel 4nm, Samsung 3nm) does not correspond to any physical dimension on the chip. This was true when Intel's 45nm node launched in 2007 and became increasingly disconnected from reality thereafter. TSMC's "3nm" node has a gate pitch (the distance between gates) of approximately 48nm — not 3nm. The naming convention became a competitive marketing metric after Intel's roadmap stalled at "10nm" for years while TSMC and Samsung advanced. The industry now uses "equivalent scaling" metrics and other figures of merit (transistor density, power efficiency, performance per watt) to meaningfully compare process nodes. When evaluating chip performance claims, look at transistors per mm² and PPAC (Power, Performance, Area, Cost) comparisons rather than the process node number.

transistor_scaling.py — compute transistor count vs process node

import math

# Dennard scaling: transistor density doubles every ~2 years (Moore's Law)
# Real transistor density data (MTr/mm²) by process node
process_nodes = {
 "Intel 22nm (2011)": 15.3,
 "TSMC 16nm (2015)": 28.2,
 "TSMC 7nm (2018)": 96.5,
 "TSMC 5nm (2020)": 173.1,
 "TSMC 3nm (2022)": 294.0,
 "TSMC 2nm (2025)": ~380.0, # estimated
}

chip_area_mm2 = 200 # mm² — typical large processor die

print(f"Transistor counts on a {chip_area_mm2}mm² die:\n")
for node, density in process_nodes.items():
 total_B = density * chip_area_mm2 / 1000
 print(ff" {node}: {total_B:.1f}B transistors")

# Output:
# Intel 22nm (2011): 3.1B transistors
# TSMC 16nm (2015): 5.6B transistors
# TSMC 7nm (2018): 19.3B transistors
# TSMC 5nm (2020): 34.6B transistors
# TSMC 3nm (2022): 58.8B transistors
# TSMC 2nm (2025): ~76.0B transistors

# Physical die size calculation
wafer_diameter_mm = 300
wafer_area = math.pi * (wafer_diameter_mm/2)**2
dies_per_wafer = wafer_area / chip_area_mm2 * 0.7 # ~70% wafer utilization
print(ff"\nDies per 300mm wafer: ~{dies_per_wafer:.0f}")

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// 02Photolithography & EUV: Printing Patterns Smaller Than a Virus

The entire logic of chip manufacturing is photographic: you create a mask (like a photographic negative) that defines the patterns you want to create on the silicon, shine light through it onto the wafer surface which has been coated with a light-sensitive material (photoresist), and develop the pattern like developing film — except the "photographs" you're taking are features that are 3 nanometers in size, and you're taking 100+ such photographs on every wafer, each aligned with nanometer precision to all the previous layers.

Traditional deep ultraviolet (DUV) lithography uses 193nm wavelength light — ArF (argon fluoride) excimer lasers. Since the minimum feature size you can print is approximately equal to the light wavelength, printing features smaller than 193nm required tricks: immersion lithography (filling the gap between lens and wafer with water, increasing effective numerical aperture), and multi-patterning (exposing the same layer multiple times with offset masks, then using etching to create features finer than any single exposure could print). TSMC's 7nm and 5nm nodes used 193nm DUV with 4-patterning — four separate exposures for a single layer. This is extraordinarily complex, exquisitely precise, and enormously time-consuming.

EUV (Extreme Ultraviolet Lithography) — the technology ASML spent €9 billion and decades developing — uses 13.5nm wavelength light, produced by firing a laser at a tin droplet at 50,000 droplets per second, vaporizing it into a plasma that emits EUV radiation. A single ASML EUV machine weighs 180 tonnes, costs €380 million (~$415M), takes a Boeing 747-freighter and multiple large cargo aircraft to deliver, and requires 40 shipping containers of support equipment. In exchange, it can print 7nm and smaller features in a single exposure that would require four DUV exposures. TSMC's 3nm node uses EUV for critical layers and DUV for less critical ones. At 2nm, EUV High-NA (next-generation with higher numerical aperture) machines become necessary for the finest features.

✅ Mask Layers: The Hidden Complexity

A modern CPU requires between 80-120 distinct mask layers — each representing a patterning step that adds, removes, or modifies material at a specific depth in the chip stack. The transistor formation alone requires ~30 layers. Metal interconnects (the wires connecting billions of transistors) require another 15-20 layers, with up to 15 metal layers stacked above the transistors. Each layer must be aligned to all previous layers with sub-nanometer precision — an error of 2-3nm in layer alignment on a 3nm process node can destroy the devices being formed. The overlay accuracy required (keeping subsequent layers aligned) is continuously improving; TSMC's EUV tools achieve <2nm overlay accuracy across a 300mm wafer.

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// 03Deposition, Etching & Ion Implantation: Building Layers Atom by Atom

Photolithography defines where materials should be added or removed, but three other process families do the actual adding and removing: deposition (putting material down), etching (taking material away), and ion implantation (modifying material properties). Together with photolithography, these four process families account for the hundreds of individual steps that transform a blank silicon wafer into a working CPU. Think of them as the build tools in a nanoscale 3D printer — except instead of printing with one material, you're building up layered structures of silicon, silicon dioxide, silicon nitride, hafnium oxide, tungsten, titanium nitride, copper, cobalt, and dozens of other materials, each with precisely controlled thickness and composition.

Chemical Vapor Deposition (CVD) introduces gases that react to form a solid film on the wafer surface. Atomic Layer Deposition (ALD) is the precision variant — it deposits exactly one atomic monolayer per cycle, alternating between two reactive gases, enabling films as thin as 1-2 nanometers with angstrom-level thickness control. The high-k gate dielectric (hafnium oxide, HfO₂) in FinFET transistors — the insulating layer between the gate electrode and the channel — is deposited by ALD at approximately 2nm thickness, equivalent to roughly 8-10 atomic layers. The precision required to make this layer exactly 2nm across a 300mm wafer, while maintaining its electrical properties, is extraordinary.

Dry etching uses plasma — a reactive gas energized into an ionized state — to chemically react with and physically remove material from the wafer surface. Reactive Ion Etching (RIE) and its variants allow highly directional etching (vertical walls, rather than the rounded profiles of wet chemical etching), which is essential for creating the sharp, precise features required at sub-10nm dimensions. The fin structure in a FinFET is formed by etching: blanket silicon is deposited, masked by photoresist defining where fins should remain, and everything else is etched away, leaving precise silicon fins protruding from the substrate. Ion implantation shoots ions (dopant atoms like boron, phosphorus, or arsenic) at high velocity into the silicon, embedding them at precise depths and concentrations to create the p-type and n-type semiconductor regions that make transistors function. The dose and energy of implantation determine the electrical characteristics of the transistors — too much or too little dopant concentration, and the transistors either don't switch or leak current.

⚠️ Thermal Budget: The Hidden Constraint in Fabrication

Here's the engineering constraint most chip manufacturing articles never mention: thermal budget. Every high-temperature step in chip fabrication (annealing to activate implanted dopants, CVD deposition, silicide formation) causes atoms to diffuse — to move slightly from their intended positions. At 3nm feature sizes, diffusion of even a few nanometers can ruin the transistors. Advanced process nodes use "spike annealing" (millisecond-scale laser or flash lamp heating to extremely high temperatures for too short a time for significant diffusion) and meticulously sequence high-temperature steps early and low-temperature steps late to prevent previously-formed features from being degraded. Managing the thermal budget — the total time-temperature exposure across all process steps — is a major constraint in process integration design.

fab_process_steps.txt — simplified CPU fabrication sequence

# Simplified FinFET CPU fabrication sequence (100+ actual steps condensed)

## 1. SUBSTRATE PREPARATION
01. Receive polished silicon wafer (300mm, p-type, CZ grown)
02. RCA clean (remove organics, native oxide, metal contaminants)
03. Deposition: grow ~10nm pad oxide (SiO₂) by thermal oxidation

## 2. FIN FORMATION
04. Deposition: SiN hardmask by CVD
05. Lithography: expose fin pattern (EUV at 3nm node)
06. Etch: RIE to form silicon fins (~40nm tall, ~6nm wide at 3nm node)
07. Deposition: shallow trench isolation (SiO₂) around fins by CVD
08. CMP: planarize to expose fin tops

## 3. GATE FORMATION (replacement metal gate)
09. Deposition: high-k dielectric (HfO₂, ~2nm) by ALD
10. Deposition: dummy polysilicon gate by LPCVD
11. Lithography + etch: define gate patterns
12. Ion implantation: source/drain extensions (boron for PMOS, arsenic for NMOS)
13. Spike anneal: activate dopants (1050°C, <1 second)
14. Remove dummy gate, replace with metal gate stack (TiN + W)

## 4. METALLIZATION (15 copper layers above transistors)
15. Via formation: lithography + etch contact holes
16. Barrier/seed: TaN/Ta barrier + Cu seed by PVD
17. Electroplating: fill vias and trenches with Cu
18. CMP: planarize copper
19. Repeat 15-18 for each of 15 metal layers
# → 100+ total steps, 80+ lithography exposures, ~6 weeks per wafer

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// 04Silicon Wafer Manufacturing: From Sand to the World's Purest Solid

Every CPU starts as silicon — the second most abundant element in Earth's crust, found in sand, quartz, and rocks everywhere. But the silicon used in chip manufacturing isn't the silicon in sand. It's silicon purified to 99.9999999% (nine 9s) purity — one impurity atom per billion silicon atoms. This "electronic grade" silicon is the purest material produced in industrial quantities on Earth. The purification process starts with metallurgical-grade silicon (98% pure, produced by reducing quartzite in an electric arc furnace), then converts it to trichlorosilane gas (HSiCl₃) and purifies the gas through fractional distillation, then decomposes the purified gas back to silicon through the Siemens process, depositing pure silicon on silicon seed rods in a reactor at 1150°C.

This purified polysilicon is then melted and grown into a single crystal by the Czochralski process: a small seed crystal is touched to the melt surface and slowly pulled upward while rotating, and silicon atoms from the melt arrange themselves in the crystal structure established by the seed. The resulting ingot is a single crystal of silicon — every atom aligned to the same crystalline orientation — roughly 300mm in diameter and 1-2 meters long, weighing 50-100kg. This is then sliced by diamond wire saws into wafers 775µm thick, and each wafer is ground, lapped, and polished to a flatness of less than 100nm across its entire 300mm surface — a smoothness 100,000 times flatter than a mirror.

The 300mm wafer format (current industry standard, introduced by TSMC and others in 2001) is a deliberate engineering choice. A 300mm wafer has about 2.3× the area of the previous 200mm standard, enabling more dies per wafer and lower manufacturing costs per chip. The next generation — 450mm wafers — was planned for the 2010s but was delayed due to the enormous capital investment required for new fab equipment at that scale. It remains a discussion point rather than an industry commitment. Every time the wafer diameter increases, the economics of semiconductor manufacturing improve dramatically — which is why this choice matters so much.

⚡ Wafer Orientation and Defect Density

The crystalline orientation of a silicon wafer matters enormously for transistor performance. The (100) orientation (with the flat wafer surface perpendicular to the crystal's [100] direction) dominates today because it enables the highest electron and hole mobility for CMOS transistors. The "notch" or "flat" on the edge of every wafer indicates its crystal orientation. Wafer manufacturers also measure the defect density — the number of crystal defects per unit area — which directly limits chip yield. A high defect density means more dies with functional defects, lower yield, and higher cost per good die. The defect density specification for leading-edge wafers is typically <0.05 defects /cm², representing extraordinary materials purity and handling precision throughout the supply chain.

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// 05Wafer Testing and Chip Binning: Sorting Good from Perfect

After six or more weeks of processing through hundreds of fabrication steps, the wafer is ready for testing — but nothing is unpacked or cut yet. Electrical test probes contact each die still on the intact wafer, running thousands of functional and parametric tests: logic functionality (does the circuit compute correctly?), speed (at what clock frequency does it operate reliably?), leakage (how much current flows when it should be "off"?), and power consumption. Each test takes milliseconds; testing an entire wafer with hundreds of dies takes hours. Dies that fail any critical test are marked — literally ink-dotted on the wafer surface in older processes, or tracked in a digital database in modern ones.

The wafer is then sawed (diced) into individual dies, and the non-failed dies are packaged — attached to a substrate, wire-bonded or flip-chip-bonded to make electrical connections, and sealed in protective encapsulation. But even among functional dies, there's a spectrum of performance. Some chips run at higher clock speeds, consume less power, or operate correctly at lower supply voltages than others — variations caused by statistical differences in doping concentrations, oxide thicknesses, and other process parameters across the wafer. Chip binning classifies these good dies into performance tiers: testing each at increasing clock frequencies until it fails, then assigning it to the product tier corresponding to its maximum reliable frequency.

This is why Intel Core i5, i7, and i9 processors often use the same silicon die: they're the same design, but i9s are the dies that tested at the highest clock speeds, i7s tested slightly lower, and i5s tested lower still. Disabled cores (in products like i5 vs i7 when i7 has more active cores) are either dies with one or two defective cores (which still function correctly with those cores disabled) or perfect dies intentionally configured lower to meet market demand for a lower-tier product. Yield — the fraction of dies on a wafer that pass testing — is one of the most closely guarded metrics in semiconductor manufacturing. A new process node typically launches with 50-60% yield and improves to 80-90%+ over 12-24 months as the fab accumulates learning and corrects process variability. Yield improvement is the primary driver of cost reduction over a node's lifetime.

⚠️ Metrology: The Invisible Process That Makes Everything Else Work

Metrology — measurement — is often overlooked in explanations of chip fabrication, but it's the feedback loop that makes every other process controllable. After every significant processing step, measurements are taken: film thickness by ellipsometry or XRR, feature dimensions by CD-SEM (critical dimension scanning electron microscopy), overlay alignment by optical overlay measurement, electrical characteristics by parametric test structures. These measurements are fed back to process control systems that automatically adjust the next wafer's process parameters to compensate for detected variations. Without metrology, process drift would accumulate over time and yield would collapse. A leading-edge fab might take more than 10,000 metrology measurements per wafer across its entire process flow.

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// synthesisThe Complete Fabrication Flow: A Six-Week Journey

A single 300mm wafer entering a leading-edge fab spends approximately 6-8 weeks in processing before emerging as packaged chips. The journey: raw polished wafer → photoresist coating → EUV or DUV exposure → development → etch or implant or deposition → strip photoresist → clean → measure → repeat for 80-120 mask layers → electrical test → dice → package → final test → bin → ship. In those 6-8 weeks, the wafer passes through 800-1,000 individual process steps, spending time in dozens of specialized tool types, each maintained at extraordinary precision.

The economics of this process are what drive the semiconductor industry's structure. A leading-edge 300mm fab costs $20-30 billion to build and equip. A single ASML EUV machine costs $415 million; a modern fab needs 10-20 of them. Equipment depreciation, labor, materials, utilities, and facility costs combine to produce a wafer processing cost of $5,000-$15,000 per wafer at advanced nodes. With 200-400 dies per wafer depending on die size, and a yield of 70-80%, the manufacturing cost per die is $20-$100 before packaging and testing. Premium die sizes (high-end CPUs and GPUs at 400-800mm² per die) have fewer dies per wafer and higher defect exposure, pushing die manufacturing costs to $200-$800+.

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// FAQFrequently Asked Questions

How are microchips manufactured step by step? + The core microchip manufacturing process follows this sequence: (1) Silicon purification and wafer growth — metallurgical silicon is purified to 99.9999999% purity and grown into a single crystal ingot via the Czochralski process, then sliced and polished into 300mm wafers. (2) Lithography — the wafer is coated with photoresist, exposed with UV or EUV light through a mask defining the circuit pattern, and developed. (3) Etch or deposition — exposed resist areas are either etched (material removed) or deposited upon (new material added). (4) Ion implantation — dopant atoms are shot into the silicon to create p-type and n-type regions. (5) Repeat — steps 2-4 are repeated 80-120 times, building up the complete 3D chip structure with transistors, contacts, and metal interconnects. (6) Testing — electrical probes test each die on the wafer. (7) Dicing — the wafer is sawed into individual chips. (8) Packaging — dies are mounted on substrates and encapsulated. The entire process takes 6-8 weeks per wafer. What is a FinFET transistor and why is it used in modern CPUs? + A FinFET (Fin Field-Effect Transistor) is a 3D transistor architecture where the silicon channel is shaped into a thin vertical "fin" and the gate electrode wraps around three sides of this fin. Traditional planar transistors had a flat channel and gate on only one side — as devices shrank below 22nm, quantum tunneling caused excessive leakage current through the thin gate oxide even when the transistor was "off," wasting energy and generating heat. FinFETs solve this by giving the gate three control surfaces around the fin, dramatically improving electrostatic control and reducing leakage by 50-100×. All modern CPUs, GPUs, and smartphone chips use FinFETs from 22nm through 3nm. The next generation, Gate-All-Around (GAA) transistors, wraps the gate on all four sides using stacked horizontal nanosheets — used in Samsung's 3nm and TSMC's upcoming 2nm processes for even better performance and leakage control. What is EUV lithography and why does it cost $415 million per machine? + EUV (Extreme Ultraviolet Lithography) uses 13.5nm wavelength light to print circuit patterns smaller than possible with previous 193nm DUV light — enabling features at 7nm and below in a single exposure vs the 4 exposures needed with DUV (dramatically reducing process complexity and cycle time). Producing EUV light requires firing a 10kW CO₂ laser at tin droplets at 50,000 droplets per second, generating a plasma that emits EUV radiation. Since no material transmits EUV (all materials absorb it), the optical system uses 11 specialized mirrors coated with alternating silicon and molybdenum layers, each polished to within 0.1nm of the target shape. The machine has 100,000 components, occupies an area the size of a large truck, weighs 180 tonnes, requires 40 shipping containers for support equipment, and represents more than 40 years of R&D investment by ASML. Only ASML manufactures EUV machines — a monopoly position that makes them one of the most strategically important companies in the technology supply chain. What is chip binning and why do CPUs have different performance tiers from the same die? + Chip binning is the process of sorting manufactured dies by their measured performance characteristics — primarily maximum clock frequency, power consumption, and number of functional cores. Statistical variations in the fabrication process (slight differences in doping concentrations, film thicknesses, feature dimensions) mean that even identically-designed dies on the same wafer have slightly different electrical characteristics. After testing, dies that can reliably operate at higher clock speeds are sold as higher-performance products at premium prices. Dies that pass functionality but run at lower speeds become lower-tier products. Dies with one or two defective cores have those cores disabled and are sold as products with fewer active cores. This is why Intel's Core i5 (6 cores), i7 (8 cores), and i9 (16 cores) can all use variations of the same basic silicon die — they're the same design sorted into different tiers based on manufacturing results. How long does it take to manufacture a CPU chip? + From raw silicon wafer to finished packaged chip takes approximately 10-14 weeks total. The wafer fabrication (front-end) phase takes 6-8 weeks and involves 800-1,000 individual process steps across 80-120 mask layers. After fabrication, wafer testing takes 1-2 days. Dicing and back-end packaging (mounting dies on substrates, adding heat spreaders, encapsulation) takes 3-5 weeks depending on package complexity (advanced 3D packaging like TSMC CoWoS or Intel Foveros adds complexity). Final electrical test and quality assurance adds another few days. The total 10-14 week cycle means chip manufacturers must start production 3-4 months before they need the finished products — a significant logistical challenge when demand changes rapidly, as happened during the chip shortage of 2020-2023. How much does it cost to build a chip fabrication plant (fab)? + A leading-edge semiconductor fabrication plant capable of manufacturing chips at 3nm or below costs $20-30 billion to build and fully equip — making it one of the most capital-intensive facilities in industry. The breakdown: the building itself (cleanroom construction, foundations, utilities) accounts for $3-5 billion. Semiconductor manufacturing equipment — lithography machines, CVD tools, etching systems, ion implanters, metrology tools, and hundreds of other specialized machines — accounts for $15-25 billion, with a single EUV lithography machine costing $415 million and a fully-equipped fab needing 10-20 units. TSMC's annual capital expenditure was approximately $36 billion in 2023, spread across multiple fab expansions and equipment upgrades. A mature fab (fully ramped on an established node) has an economic lifetime of 10-15 years, during which the enormous capital investment must be recovered through wafer revenue. What does the nm number in CPU process nodes actually mean? + In modern semiconductor marketing, the "nm" number in process node names (TSMC 3nm, Intel 4nm, Samsung 3nm) no longer corresponds to any specific physical dimension on the chip. This disconnect from physical reality began in the early 2010s and became complete by the 7nm generation. TSMC's "3nm" node has a contacted gate pitch (the spacing between gate centers) of approximately 48nm — not 3nm. The naming convention became a competitive metric: companies wanted their nodes to sound more advanced than competitors'. The meaningful metrics for comparing process nodes are: transistor density (transistors per mm²), SRAM bit cell area, standard cell height, and PPAC (Power, Performance, Area, Cost) comparisons at standardized workloads. TSMC N3 (their "3nm" node) delivers approximately 1.7× the transistor density of their N5 ("5nm") node — that 1.7× density improvement is the meaningful measure of advancement, not the node name. What makes semiconductor manufacturing cleanrooms so clean? + Semiconductor cleanrooms use a combination of HEPA/ULPA air filtration, positive air pressure, laminar flow (air flows uniformly downward from ceiling to floor rather than turbulently), strict gowning protocols, and rigorous material controls to achieve cleanliness ratings of ISO Class 1-3 (the cleanest categories). The air is recirculated 500+ times per hour through filters that capture particles down to 0.01µm. Workers wear "bunny suits" — full-body coveralls, gloves, boots, and respirators that prevent human-shed particles (skin cells, hair, clothing fibers) from reaching the wafer environment. The reason for this extreme cleanliness: a particle 0.1µm across landing on a wafer being patterned at 3nm scale is the equivalent of a house landing on a street — it would destroy every device in the area of contamination. Even a single stray particle reaching a wafer can ruin dozens of dies worth thousands of dollars.

🔬 Semiconductor Fab Lab

Four experiments: lithography layer visualizer, FinFET cross-section, wafer yield calculator, and chip economics.

Click ▶ to step through a photolithography cycle — coat, expose, develop, etch

// Photolithography Simulator Process node 3nm (EUV) Layer number 1/80 1 Exposures/layer 13.5nm Light wavelength 3nm Min feature size $415M Tool cost

Cross-section of a FinFET transistor — adjust dimensions to see structure changes

// FinFET Cross-Section Builder Transistor type FinFET Gate length (nm) 12nm — Gate control surfaces — Leakage vs planar — Typical process node — Next evolution

300mm wafer with dies — click to toggle defects. Green = good die, Red = failed

// Wafer Yield Calculator Die size (mm²) 150mm² Defect density (def/cm²) 0.05 — Dies per wafer — Yield % — Good dies — Cost per good die

Cost breakdown per chip: wafer cost, yield loss, packaging, test

// Chip Economics Calculator Process node TSMC 3nm Die size (mm²) 200 Yield (%) 75% — Dies per wafer — Manufacturing cost/die — Total cost (+ pkg + test) — Est. retail multiple